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1970s Design Indulgence

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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 19 Jul 2018 at 1:21am
We all know in low noise high performance circuitry to keep wiring as short as possible...


But every circuit has to be tried before committing to expense!

Hooked up to the AP it did 67dB S/N (CCIR 20Hz - 20kHz) and 0.01% THD and 50mV max input on a 30V lab power supply.

In reality hooked up to an Ortofon 2M Bronze it's a bit buzzy due to the less than ideal S-Dec lash-up and zero shielding.

Still, it sounds quite nice. In fact I'd best not say too much Wink

I replaced the simple BC337's with BC184C's (discontinued these days) to obtain more bandwidth, but it didn't fully succeed. If it ever reached production I would have to use BC237's.

More on the theory as promised next up.

By the way, this is neither of the designs recently discussed, but close. It uses 4 transistors per channel.

Actually, I have to say it does sound shockingly good Shocked





Edited by Graham Slee - 19 Jul 2018 at 1:31am
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 19 Jul 2018 at 2:32am
If we closely examine HPW's circuit with DS's circuit we can see DS has omitted the potential divider of HPW in the first transistor's collector load supply.

This translates to DS's Q1 running at a higher collector current (or emitter current as some would have it) than that of HPW. About 3.5 times.

If we increase the current in Q1 (TR1) the dominant pole capacitor (C4 HPW; C1 DS) must be increased in value to match.

Here we find HPW's slew rate is 8.5V/uS from V/T = I/C, and if DS's circuit is to be believed its slew rate is 30V/uS.

In my opinion it is an error of omission, and the value should be 18 pF or perhaps more.

But is either circuit immune to slew induced distortion (SID for short)?

The linearity of the input transistor plays its part, and here it is operated in transconductance mode, where the only emitter degeneration is its intrinsic emitter resistance.

It might be argued that the NFB divider resistor (R7: 470R in both diagrams) provides emitter degeneration, but does it?

The emitter is the input for negative feedback. Think of the input being the 470R resistor, but taken to ground instead. It is the equivalent of a long-tail pair without emitter resistors. Therefore R7 doesn't provide emitter degeneration, or if it does, it isn't very linear versus frequency because of the RIAA network's impedance being essentially in parallel with it.

If we took the differential slew rate formula from the Art of Electronics as 0.3Ft we will see it is nowhere near 8.5V/uS (a guesstimate is around 2MHz for Ft). OK, that formula isn't exact here because it is not a differential input, but gives us some idea.

This phenomena is due to the limitation of input linearity of the bipolar transistor base: 60mV p-p, or 30mV peak. Above that TR1/Q1 saturates and the input has to drive the dominant pole capacitor directly (the 4.7pF capacitor). This slew limits the input causing transient distortion.

What is needed is some emitter resistance between the emitter and R7 (and the lower end of the RF filter cap moves up to the emitter).

At 40uA the intrinsic resistance is 625 Ohms (25mV at 20 C divided by emitter current) which isn't too bad, but varies with temperature. At 140uA (DS circuit) it is about 180 Ohms.

If we swamp 180 Ohms by adding say a 1.5k resistor, we obtain a multiplier or a 9 times improvement over the DS circuit. We can approach 4.5V/uS or thereabouts. It all depends on Ft - the frequency where the stage falls off to unity gain and its stability.

However, this adds to noise, and we have to consider which is best: more musical realism or something that's dead quiet when not in use?

It also reduces open-loop gain which has to be made up for elsewhere, and this is why my circuit has an extra transistor.

More to follow.
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 21 Jul 2018 at 1:13am
Here's my test circuit...

transistor preamp test circuit

And here's how it works

Part 1: Biasing

To operate linearly a silicon transistor is biased to approx. 0.6V VBE. Some iteration is required in establishing resistor values, and fine tuning is adjusted on test for a symmetrical output signal swing, but to start we estimate voltages around the circuit.

We want somewhere in the region of 100uA in T1. Lower current improves S/N, and higher current improves distortion (you can have one or the other but not both).

With the values chosen I estimated about 127uA, which is the voltage from the supply to T1 collector divided by R4+R5. This 127mA flows in R6 and R7 making T1 emitter voltage 0.24V.

Add on 0.6V VBE and the voltage on T1 base needs to be approx. 0.84V. This is derived from potential divider R8/R3 making T3 emitter voltage approx. 3.45V, which is the voltage across R12 and we find its emitter current is 0.8mA. This sets the voltage drop across R10+R11 at 10V, but base current for T4 also flows along this path.

T4 emitter needs to swing half of 30V minus T3 emitter voltage, or half 26.5 volts which is 13.25V to which is added T3 emitter's 3.45V making 16.7 volts. T4 base is therefore (16.7V + 0.6V) 17.3V. T4 emitter current is 16.7V divided by R15+R16, which is 7.2mA.

Using a power amp output stage driver transistor for T4, which has a current gain of approx. 100, we see T4 base current is approx. 72uA. This is added to T3 collector current making the voltage drop across R10+R11 nearly 11V.

The voltage drop across R14 is 72uA x 10k = 0.72V.

We now add 17.3V, 11V and 0.72 volts and we should have the 30V supply voltage. It works out at 29.02V, but DC negative feedback around the circuit will correct for that, and in doing so make T4 emitter voltage slightly higher so everything balances out.

I conveniently left out T2 from the calculations because its current flows back into T3 base, thus cancelling its effect as far as biasing is concerned.

However, T2 combined with T3 contribute two VBE drops (1.2V), and if T3 emitter is 3.45V, T2 base must be 4.65V. 30V - 4.65V gives 25.35V which appears across R4+R5, and 25.35V/200k = 127uA. Good estimate!
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 22 Jul 2018 at 4:34am
Above I said "Lower current improves S/N, and higher current improves distortion" but on other occasions it's the opposite. Here I should have mentioned 'lines of constant noise', but I didn't because it could get a little too deep. So what I am explaing here applies to what I'm doing here, and not in general. This is probably why I don't teach electronics...
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 22 Jul 2018 at 6:04am
Part 2: (what shall we call part 2?)



So what's the value of R1? 47k? No way!

But that's the load an MM cartridge wants to see.

Signal is ac (small letters if you're talking alternating current - signal current). The ac is passed by capacitors where DC is blocked.

C1 is therefore a "piece of wire" to ac, and so R1 is in parallel with R3 and R8. Why R8? Because C8 is also a "piece of wire" to ac and so R8 connects to ground.

So these three values must equate to 47k (1/47k = 1/R1 + 1/R3 + 1/R8).

But shouldn't we include the input resistance to T1?

Great question!

The signal on T1 base is the same(ish) as the signal on T1 emitter (only the current is different). So if the signal is rising on the base, it is also rising on the emitter. Its diode junction is simply following - it's an emitter follower.

The circuit output is n-times the input decided by the negative feedback ratio of the lumped C5, C6, R9, R13, divided by R7.

This being fed back by the output and being the same way up, the emitter signal is also rising. It is rising by the same as the base, so any resistance there could be has no effect, so it doesn't exist as far as the signal is concerned.

Therefore, the ac input resistance (we should call it impedance because it's ac) is just R1, R3 and R8 in parallel.

There is always a BUT though. And the BUT here is that emitters don't really follow, and feedback signals don't appear at exactly the same time as the input.

The base-emitter diode junction isn't perfect so the signal appearing on the emitter isn't exactly the same as that on the base, but it is very close.

All active devices (like transistors) have rise times. They cannot respond instantly, although they are really fast, and shouldn't be a problem, but they are.

And also the dielectric of capacitors C5 and C6 can alter the signal "quality", so the negative feedback isn't a perfect match to the input, but it is very near.

So these three things can be ignored? If you want... And the earlier circuits did ignore them, and that's why transistors got bad press (and Mr Self moved onto "the far superior" op-amps).

And so we come to R6. Let's assume that one or all three of these occurrences were to happen. R7 would effectively not exist as we think of it. Say we replaced it by a wire link (this being an absolute worse scenario).

T1 would then have input resistance in parallel with the composite 47k (R1,R3,R8), taking it below 47k and messing up the highs (at least).

The actual value is hfe times intrinsic emitter resistance of T1. hfe varies between one transistor and the next, and intrinsic emitter resistance is temperature sensitive. But given that we might have a transistor with hfe of say 360 and that the temperature is 20C, we take the emitter diode junction thermal voltage as 25mV and divide it by its current which is 127uA.

Here goes: 25/0.127 = 197 Ohms. Multiply by 360 = 71k Ohms.

So we have around 70k in parallel with our 47k making 28k. That messes up the cartridge response no end.

However, this is worse case, but Murphy's law is good to remember...

How do we ensure our load doesn't dip so low? The answer is R6. It adds 1.5k to the 197 Ohms, and this is multiplied by hfe (360 here), making it 611k Ohms instead of 70k Ohms.

It can now dip worse case to 44k and you'd be hard pressed to hear that for the nano-seconds involved.

R6 has a couple of faults: 1. it is a noise source like all resistors, and adds 6nV per root hertz (0.864uV of noise 20Hz - 20kHz, so we might have to do a bit of tweaking here); and 2. it reduces the stage gain to R5/(R6+R7) which is 53 (usually it would be around 500).

Also, even though R6 is local negative feedback, it doesn't reduce distortion.

The next stage which is T2, T3, is usually just one transistor. It's emitter is connected to ground at ac, so its input resistance is (again) hfe times intrinsic emitter resistance. Because more current flows (0.8mA from our bias calculations) we get R-emitter = 25/0.8 = 31 Ohms, and if hfe is 360 again, R-in = 11k.

The output impedance of T1 is R5, 100k, so there is signal attenuation due to the potential divider action of 100k/11k +1, which divides by 10. So all we got so far is a gain of 53 reduced to 5.3, which is terrible!

By adding a transistor, here as a "darlington" or "super-beta" arrangement, we increase the load resistance by the additional hfe, and it will be around 3 MegOhms. Our stage gain is therefore going to be around 50 - 52, which is what it would be in the three transistor circuits that don't use R6.

But the beauty of R6 is that it increases input latitude so that any big fast input signal doesn't get "squashed" which would effectively reduce slew-rate and cause SID (slew induced distortion), and if that were a click, it would be over-emphasised. This is how we reduce clicks!

So what is the slew rate? If V/T = I/C (which it does), then 127uA/22pf = 5.77V/uS (127uA is the collector current in T1 which charges the 22pf which is the dominant pole capacitor between T2,T3 collector and base).

Part 3 to follow.




Edited by Graham Slee - 22 Jul 2018 at 6:14am
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Post Options Post Options   Thanks (0) Thanks(0)   Quote Graham Slee Quote  Post ReplyReply Direct Link To This Post Posted: 22 Jul 2018 at 2:06pm
Part 3: Stability

All transistor specifications state Ft, the frequency at which their hfe (or beta, or current gain) reaches unity. They're not much use at that frequency. And at 20dB per decade you have to come down several decades to hit the hfe you're after.

A 100MHz transistor having a common hfe of 200 will only be that 2.5 decades lower at 40MHz, and most small signal transistors have real hfe's more than that. So let's make the maximum bandwidth we're aiming for below 10MHz - it makes sense.

Each transistor also has input capacitance which tries to attenuate the previous stage's bandwidth.

Once we add a negative feedback loop an uncompensated amp can turn into an oscillator, so we need to bring down the stage's bandwidth sufficiently to avoid this, and this is the function of C4.

In this circuit we have the added problem of T4 which, as an emitter follower as it is configured here, also make accidental Colpitts oscillators.

Any inductance on its base tends to start it oscillating. Here we use R14 and C7 tuned to stop T4 oscillating (a bit like a valve grid-stop). We also isolate T4's output with resistors R15 to the NFB and R17 to the outside world.

Even so we will see from the frequency versus phase plot the tendency for the circuit to come back up at around 200MHz, just where the average of Ft's is for our bunch of transistors.

If we keep this a factor of 10 below unity gain (gain margin) then it's pretty safe that it won't do anything silly. A lot of involved math would be needed to work this out the old 1970s way so computers started to be used to do the number crunching, and a program called SPICE came on the scene in 1973, but it took a fair few number of years to be adopted.

Most calculations look at high frequency stability missing some crazy things that can happen in the bass. The following is the plot of this circuit and a third curve was added to show the effect of the T4 bootstrap C9 if the lows are not considered. Nice bass!?



Plot shows:

1. upward bass kink at 2Hz for not observing phase shifts: plenty of cone flap with this!
2: between 20Hz to beyond 100kHz the RIAA replay response.
3: the extent of bandwidth where it crosses 0dB and it's safe phase margin - over 90 degrees
4: gain margin at 180 degrees better than a factor of 10 (20dB)
5: the transistor's combined Ft's "hump" above 100MHz where they would oscillate if not for precautions
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Post Options Post Options   Thanks (0) Thanks(0)   Quote BAK Quote  Post ReplyReply Direct Link To This Post Posted: 22 Jul 2018 at 11:00pm
Originally posted by Graham Slee Graham Slee wrote:

Part 2: (what shall we call part 2?)

How about "Real Input Impedance" and "Feedback concerns"


Edited by BAK - 23 Jul 2018 at 12:05am
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